The subject matter of this disclosure relates generally to electronic gate drive circuits and more particularly to a system and method for providing a high speed, low loss gate drive circuit for semiconductor switches such as, without limitation, metal oxide semiconductor field effect transistor (MOSFET) switches, insulated gate bipolar transistor (IGBT) switches, and thyristor switches.
Turn-on and turn-off speeds of some types of semiconductor switches such as MOSFET switches and IGBT switches are disadvantageously limited by R-C circuit elements when employed in conventional voltage source gate drive circuits. Such voltage source gate drive circuits further suffer from lost gate charge.
As shown in FIG. 1, a conventional gate driver circuit 10 is typically implemented in an IC that consists of a pair of N and P-channel low voltage MOSFETs. When the control signal Vsig turns on the upper P-channel MOSFET, a charging current goes from Vc through a gate resistor Rg, internal gate mesh resistance Rg_i, to charge up the gate input capacitance, CISS (=Cgs+Cgd), of the power switch, SW, causing it turn on. When the control signal Vsig turns off the P-channel switch and turns on the lower N-channel switch, a discharging current discharges the input capacitance thereof and the SW is turned off.
Although the conventional gate driver ICs are easy to use, they usually suffer from two major issues. One issue is related to the gate driver power losses and the other is related to the operation modes of the power switch they drive. Since the resistance is in the charging and discharging path the gate driver loses approximately twice the energy stored in the power switch's input capacitance each time the switch goes through an on and off cycle. Therefore the gate driver power loss is simply proportional to the operation frequency. Nevertheless high frequency operation provides fast transient response, small component size and superior power density.
There is a steady trend to increase converters' switching frequency continuously over the past decades. The gate driver loss becomes a limiting factor when the operation frequency enters MHz region. Thanks to the great demand on the computer and telecommunication power converters, significant efforts have been made to find innovative ways to reduce the gate driver losses. A fair amount of reference papers and patents can be found in literature, such as Steigerwald, Robert L. (Burnt Hills, N.Y.) U.S. Pat. No. 5,010,261, “Lossless gate driver circuit for a high frequency converter,” Maksimovic, D.; “A MOS gate drive with resonant transitions,” IEEE PESC '91 Record, Page(s): 527-532, Yuhui Chen; etc. “A resonant MOSFET gate driver with efficient energy recovery,” IEEE Transactions on Power Electronics, Volume: 19, Issue: 2, 2004, Page(s): 470-477, de Vries, I. D.; “A resonant power MOSFET/IGBT gate driver,” IEEE APEC 2002. Page(s): 179-185 vol. 1, Faye, Li, U.S. Pat. No. 6,650,169, “Gate driver apparatus having an energy recovering circuit,” Inoshita, Ryousuke (Nishikamo-gun, JP), U.S. Pat. No. 7,091,753, “Gate driving circuit,” Omura, Ichiro (Yokohama, JP), U.S. Pat. No. 7,459,945, “Gate driving circuit and gate driving method of power MOSFET,” Yang, Zhihua (Kingston, Calif.), Liu, Yan-fei (Kingston, Calif.), U.S. Pat. No. 7,612,602, “Resonant gate drive circuits,” etc., to name a few.
The above mentioned references mostly achieve the goal of lowering gate driver losses. They, however, lack a systematic approach to deal with the issues associated with the power switch operation modes where the effects of parasitic components as well as transient and extreme operating conditions are important.
FIG. 2 shows a half-bridge model 20 with important parasitic components included. The half-bridge configuration is widely used in applications such as high power hard or soft switching, high frequency low voltage synchronous rectifier power supplies, and soft switching resonant converters. It also represents a so-called clamped inductive switching model where most MOSFET transistors and high speed drive circuit work in that operating mode.
The turn-off procedure of the power switches can be roughly categorized into four time intervals: 1) turn-off delay interval where CISS is discharged from its initial value to the Miller plateau level; 2) Miller plateau interval where the drain-to-source voltage rises from IDRDS(on) to the final VDS(off) level clamped by the body diode of the complementary switch and the gate current is strictly discharging Cgd; 3) linear interval where the gate voltage resumes falling from VGS,Miller to Vth and the drain current of the power switch decreases following the declining of gate-to-source voltage; 4) fully off interval where the CISS is fully discharged.
The turn-on procedure is back tracking the turn-off steps. It is intuitively obvious that switching losses exist due to high current and high voltage being present in the power device simultaneously for a short period corresponding to the Miller plateau interval when the drain voltage goes through its switching transient and linear interval when the drain current changes responding to the change in the gate voltage. It becomes essential to shorten these two intervals to reduce the switching losses of the power switch.
In practical applications, the effects of parasitic components and dv/dt limits have to be taken into account since the shapes of the current and voltage, as well as the switching times during the switching procedure are altered significantly when the parasitic inductive components come into play. The dv/dt limit of the power switch sets the up speed limit of the switching transient time. The dv/dt limit describes an unintentional turn-on phenomenon caused by the current flowing through the gate-drain capacitor and generating a positive gate-to-source voltage when the drain-to-source voltage rises rapidly. Since the turn-on threshold voltage Vth changes with an approximately −7 mV/° C. temperature coefficient, MOSFET transistors are more susceptible to dv/dt when operating at elevated temperature. Therefore the effect of high junction temperature must be taken into account.
As discussed herein, the parasitic inductive components alter the current and voltage waveforms that exhibit a profound effect on switching performance. The most important parasitic inductive components are the source inductance LS and drain inductance LD as shown in FIG. 2. The source inductance LS not only causes the oscillatory spikes observed in most gate drive circuit, it also shows a negative feedback effect whenever the drain current of the device is changing rapidly. This feedback mechanism establishes a delicate balance of gate current and drain di/dt. The drain inductance LD on the other hand acts as a beneficial turn-on snubber but produces an overshoot in the drain-to-source and an increase in turn-off switching losses.
To further improve gate driver performance, it is important to recognize that gate driver turn-off capability has a more profound impact on the power device switching losses, dv/dt limit and di/dt EMI performance than the turn-on characteristic does, especially in the typical application shown in FIG. 2. In the hard switching case the turn-on speed is usually limited by the turn-off, or reverse recovery speed of the diode, and not by the strength of the gate drive circuit. Therefore, it is beneficial to match the diode switching characteristics.
In a zero-voltage-switching case, the Miller effect is not present since the drain-to-source voltage is practically zero when the gate is turned-on, or the turn-on of power switch starts with the turn-off of the other complementary power switch. The turn-off speed of the power MOSFET on the other side depends almost solely on the gate drive circuit. The gate driver circuit, however, is required to handle the maximum dv/dt that can occur under worst case conditions; for example, most resonant and soft switching converters can force a dv/dt across the power switch right after its turn-off instance due to the power stage resonant components.
It would be both advantageous and beneficial to provide a high speed, low loss gate drive circuit that overcomes the foregoing disadvantages generally associated with conventional voltage source gate drive circuits.